An application such as a set-top box can communicate with other media devices around the home. For example, it can download content to an iPod, interact with the home PC, or have an internet connection. These involve communication over different medium using different security protocols. In such security protocols, cryptography requires very intensive arithmetic which is time consuming for an embedded processor that typically has to respond to many interrupts from other functional blocks within the STB SoC. Our research investigates adaptable processor architectures that can be used to provide a means to offload the intensive arithmetic. Recent work in this area has included the design of two suitable architectures to support public and private key algorithms.
Adaptable, Scalable Public Key Cryptographic Processor Architecture
- Supports integer and polynomial arithmetic & optimised instructions that provide efficient field multiplication, addition and inversion
- Support of algorithms which include modular exponentiation (RSA), ECC over prime fields & ECC over binary fields
- Field & operand lengths only restricted by data RAM provided
(previous designs have fixed field lengths)
Private Key RISC Microprocessor Architecture
Includes:
- Algorithm specific instructions: eg. GF Multiplication
- An extended Instruction set: common algorithm Bit-oriented & Byte-oriented instructions
- Co-processors of common algorithms eg. AES and DES
- Private Key RISC Microprocessor Architecture
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